When electronic hardware is used to realize a neural network, the amount of information communicated among processor elements increases, especially when a high degree of parallel processing is applied with the large number of processor elements. In this case, communication delays become large.
On the other hand; in order to accelerate communication while maintaining the degree of parallel processing, it is conceivable that multiple processor elements may be formed in a single LSI. However, that single LSI cannot comply a large portion of a network because the conditions are fixed between processor elements in LSI.